The iPSC-2 was also a hypercube-based machine, but it incorporated ``worm-hole routing'' in place of the store and forward packet switching used in earlier systems. A worm-hole router uses a form of circuit switching to establish a communication path between two processors according to fixed rules. For example, in the two dimensional mesh the rule might be to use the vertical links first until the row of processors containing the destination processor is reached and to then use the horizontal links until the connection is made. Efficiency is improved because the technique removes the requirement that each processor along a route makes a decision about the direction of the next step of the communication. This in effect reduces the dependence of the diameter of the array on the number of steps required to transmit a data item from one end of the system to the other. What one gains in efficiency one loses in flexibility because worm-hole routing eliminates the opportunity to use alternate paths that might be provided by the network. For example, congestion on a single link may be unavoidable even though alternate paths are available to ease the congestion.
Following the iPSC/2 (and the iPSC/860, which was similar but used i860 RISC processors instead of 80386 processors at each node), Intel built a research machine known as the Touchstone Delta. A commercial system based on the Delta is the Paragon XP/S. The interconnection network is a 2D mesh instead of a hypercube, and uses specially designed message routing chips to improve communication bandwidth. Each node in the Paragon has two i860 processors, one for computation and the other for message handling. This second processor deals with incoming messages and other overhead so the main processor does not have to be interrupted to handle message traffic.