In an interleaved memory, the memory is divided into a set of banks. An interleaved memory with n banks is said to be n-way interleaved. One way of allocating virtual addresses to memory modules is to divide the memory space (the set of all possible addresses a processor can generate) into contiguous blocks. If there are n banks, memory location i would reside in bank number (ignoring remainders). In an interleaved memory, however, consecutive addresses reside in different banks: memory location i is in bank number . For example, suppose there are 4 banks, each containing 256 bytes. The block-oriented scheme would assign virtual addresses to the first bank, to the second bank, and so on. The interleaved scheme would assign addresses 0, 4, 8, to the first bank, 1, 5, 9, to the second bank, etc. (Figure 6).
However the memory space is split up among the banks, as long as requests are sent to two different banks they can be handled simultaneously. The processor can request a transfer from location i on one cycle, and on the next cycle request information from location j. If i and j are in different banks, the information will be returned on successive cycles. Note that the latency of the request, i.e. the number of cycles a processor has to wait before receiving the contents of location i, is not affected. However the bandwidth is improved; if there are enough banks the memory system can potentially send information at a rate of one word per processor cycle, regardless of what the memory cycle time is.
Figure 6: Interleaved Memory.