2.1 Processors



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2.1 Processors

 

The operation of a processor is characterized by a fetch-decode-execute cycle. In the first phase of the cycle, the processor fetches an instruction from memory. The address of the instruction to fetch is stored in an internal registergif named the program counter, or PC. As the processor is waiting for the memory to respond with the instruction, it increments the PC. This means the fetch phase of the next cycle will fetch the instruction in the next sequential location in memory (unless the PC is modified by a later phase of the cycle).

In the decode phase the processor stores the information returned by the memory in another internal register, known as the instruction register, or IR. The IR now holds a single machine instruction, encoded as a binary number. The processor decodes the value in the IR in order to figure out which operations to perform in the next stage.

In the execution stage the processor actually carries out the instruction. This step often requires further memory operations; for example, the instruction may direct the processor to fetch two operands from memory, add them, and store the result in a third location (the addresses of the operands and the result are also encoded as part of the instruction). At the end of this phase the machine starts the cycle over again by entering the fetch phase for the next instruction.

Instructions can be classified as one of three major types: arithmetic/logic, data transfer, and control. Arithmetic and logic instructions apply primitive functions of one or two arguments, for example addition, multiplication, or logical AND. In some machines the arguments are fetched from main memory and the result is returned to main memory, but more often the operands are all in registers inside the CPU. Most machines have a set of general purpose registers that can be used for holding such operands. For example the HP-PA processor in Hewlett-Packard workstations has 32 such registers, each of which holds a single number.

The data transfer instructions move data from one location to another, for example between registers, or from main memory to a register, or between two different memory locations. Data transfer instructions are also used to initiate I/O operations.

Control instructions modify the order in which instructions are executed. They are used to construct loops, if-then-else constructs, etc. For example, consider the following DO loop in Fortran:

          DO 10 I=1,5
          ...
10        CONTINUE

To implement the bottom of the loop (at the CONTINUE statement) there might be an arithmetic instruction that adds 1 to I, followed by a control instruction that compares I to 5 and branches to the top of the loop if I is less than or equal to 5. The branch operation is performed by simply setting the PC to the address of the instruction at the top of the loop.

The timing of the fetch, decode, and execute phases depends on the internal construction of the processor and the complexity of the instructions it executes. The quantum time unit for measuring operations is known as a clock cycle. The logic that directs operations within a processor is controlled by an external clock, which is simply a circuit that generates a square wave with a fixed period. The number of clock cycles required to carry out an operation determines the amount of time it will take.

One cannot simply assume that if a multiplication can be done in nanoseconds then it will take nanoseconds to perform multiplications or that if a branch instruction takes nanoseconds the next instruction will begin execution nanoseconds following the branch. The actual timings depend on the organization of the memory system and the communication channels that connect the processor to the memory; these are the topics of the next two sections.



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Next: 2.2 Memories Up: 2 Basic Computer Architecture Previous: 2 Basic Computer Architecture



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