3.1.1 SISD Computers



next up previous
Next: 3.1.2 SIMD Computers Up: 3.1 Flynn's Taxonomy Previous: 3.1 Flynn's Taxonomy

3.1.1 SISD Computers

 

Conventional single processor computers are classified as SISD systems. Each arithmetic instruction initiates an operation on a data item taken from a single stream of data elements. Historical supercomputers such as the Control Data Corporation 6600 and 7600 fit this category as do most contemporary microprocessors.

Vector processors such as the Cray-1 and its descendants are often classified as SIMD machines, although they are more properly regarded as SISD machines. Vector processors achieve their high performance by passing successive elements of vectors through separate pieces of hardware dedicated to independent phases of a complex operation. For example, in order to add two numbers such as and , the numbers must have the same exponent. The processor must shift the mantissa (and decrement the exponent) of one number until its exponent matches the exponent of the other number. In this example is adjusted to so it can be added to , and the sum is . A vector processor is specially constructed to feed a data stream into the processor at a high rate, so that as one part of the processor is adding the mantissas in the pair another part of the processor is adjusting the exponents in .

The ambiguity over the classification of vector machines depends on how one views the flow of data. A static ``snapshot'' of the processor during the processing of a vector would show several pieces of data being operated on at one time, and under this view one could say one instruction (a vector add) initiates several data operations (adjust exponents, add mantissas, etc.) and the machine might be classified SIMD. A more dynamic view shows that there is just one stream of data, and elements of this stream are passed sequentially through a single pipeline (which implements addition in this example). Another argument for not including vector machines in the SIMD category will be presented when we see how SIMD machines implement vector addition.



next up previous
Next: 3.1.2 SIMD Computers Up: 3.1 Flynn's Taxonomy Previous: 3.1 Flynn's Taxonomy



verena@csep1.phy.ornl.gov