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3.1 Architecture

The MasPar MP-2 comes in sizes of 1024, 2048, 4096, 8192 or 16384 processors in its processor element (PE) array. The MP-2 at UTK/JICS has 4096 processors, and we will refer to this machine from here on, unless specifically stated otherwise. A 12-MIPS R (ACU) controls the PE array; it has its own memory for data and instructions.

Every PE receives the same instruction from the ACU simultaneously. Only those processor elements located in the active set, which can be user-defined, carry out instructions received from the ACU. Each of the PEs are 32-bit ALUs under the control of the ACU, with 64 KB of memory and sixty-four 32-bit registers. Both the ACU and the PE array are contained in the DPU, or Data Parallel Unit, which is where all parallel processing is performed. The front end of the MP-2 is a DEC 5000/200 workstation, currently running under Ultrix v4.2a. This front end provides user access to the ACU.