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3.2 Pipelines     continued...

A very important requirement for overlapping operations this way is that there be no resource conflicts, i.e. the operands must be independent. For example, suppose a program contains the two instructions

R2 = R0 + R1  
R4 = R3 + R1

Note that both instructions identify R1 as one of their inputs. There is a potential conflict in stages two and three of the adder pipeline because stage two might need to shift the mantissa of R1 at the same time stage three needs to add the mantissa of R0 to the mantissa of R1. The solution is to make copies of the operands, and pass the copies through the pipeline. Thus the CPU gives the adder copies of R0 and R1 when it starts the pipeline for the first pair, and the second stage gets these copies from the first stage along with a value of .

There is another potential problem illustrated by this example. Suppose the second instruction is changed so one of its operands is R2, so the pair of instructions is:

R2 = R0 + R1
R4 = R2 + R1

Now the second instruction depends on the result of the first instruction. The CPU cannot send the second pair of operands to the pipelined adder until the result of the first addition exits the last stage of the pipeline. Interactions such as these lead to periods when pipeline stages are empty. These empty time slots are often called bubbles.